1. Field of the Invention
The present invention relates to a wiring board and more particularly relates to a wiring board including wiring for connecting terminals included in one of a plurality of semiconductor chips to terminals included in another one of the plurality of semiconductor chips, through branch points.
2. Description of the Related Art
There are a wide variety of electronic devices that implement one-to-many connection between a plurality of semiconductor chips, for example, between one memory controller chip and a plurality of random access memories (hereinafter referred to as RAMs), all of which are mounted on a board. Such boards include a board having a plurality of semiconductor chips or semiconductor modules mounted thereon, such as a semiconductor package board, a printed circuit board, a system-in-package board and a multichip module board.
In the connection between a memory controller chip and a plurality of RAM chips, wiring for a plurality of signals on data, address, clock, clock enable and chip select are drawn out by bus wiring method, branched in the middle and connected to the plurality of RAM chips. In order to complete, within the board, functions of such a system including two kinds of chips, the memory controller chip and the RAM chips, it is preferable that all the bus wiring paths between the memory controller chip and the RAM chips be set to have an equal length, thereby eliminating a phase difference due to wiring delay in signal transmission.
Japanese Patent Application Laid-open No. 2004-119454 (Patent Document 1) discloses a printed circuit board in which all wires in a bus wiring are set to have an equal length. FIGS. 3A and 3B are views schematically showing a structure of the printed circuit board disclosed in the Patent Document 1. FIG. 3A is a plan view. In FIGS. 3A and 3B, one memory controller IC 102 and two RAMs 103 and 104 are mounted on a printed wiring board 100. The printed wiring board 100 is a semiconductor package board including two layers, which are a front-side and a back-side layers, each layer having wiring. Reference numeral 110 denotes a bus wiring path which connects the memory controller IC 102 to the RAM 103. The bus wiring paths 110 are provided on the front-side layer of the printed wiring board 100. Reference numeral 111 denotes a bus wiring path which connects the memory controller IC 102 to the RAM 104. The bus wiring paths 111 are respectively provided by branching the bus wiring paths 110, which are extended from the memory controller IC 102, at vias 120 and are connected to the back-side layer of the printed wiring board 100. The bus wiring paths 110 and 111 are line-symmetrically drawn out toward the RAMs 103 and 104, respectively, from the vias 120 to be branch points. Moreover, the bus wiring paths 111 are routed back to the front-side layer of the printed wiring board 100 through vias 121 and are connected to the RAM 104.
Here, in the bus wiring paths 110, the positions of the vias 120 are determined so that the wires from the vias 120 to the memory controller IC 102 can be parallel to each other and have an equal length. Moreover, the positions of the vias 120 are determined so that the length of the each wire from the corresponding via 120 to the RAM 103 in the bus wiring paths 110 and the length of each wire from the corresponding via 120 to the RAM 104 in the bus wiring paths 111 can be linearly equal to each other. Since the RAMs 103 and 104 are identical RAM chips, the wires are connected to the RAM 103 at identical positions where the wires are connected to the RAM 104. Therefore, the vias 120 are disposed at middle points between the RAMs 103 and 104 while the series of vias 120, the RAMs 103 and 104 are arranged in parallel with one another.
FIG. 3B is a perspective view schematically showing the printed circuit board shown in FIG. 3A. The printed circuit board has the structure in which the length of each wire from the via 120 to the RAM 103 in the bus wiring paths 110 and the length of each wire from the via 120 to the RAM 104 in the bus wiring 111 are set to be equal to each other. However, with reference to FIG. 3B, the length of each wire leading from the vias 120 to the RAM 103 and the length of each wire leading from the via 120 to the RAM 104 are not completely equal. Specifically, in the wiring paths from the memory controller IC 102 to the RAM 104, the vias 120 and 121 are used to provide wiring to connect the front-side and back-side layers. Therefore, the wiring length from the memory controller IC 102 to the RAM 104 is longer than the wiring length from the memory controller IC 102 to the RAM 103 by the lengths of the vias 120 and 121.
Meanwhile, there has recently been an increasing demand for higher-speed memories up to beyond gigabit speed. Accordingly, great importance has been placed on the impact of wiring delay on signal transmission. Thus, there is an increasing need to set all the bus wiring paths between the memory controller chip and the RAMs to have an equal length. However, according to the conventional technology, the lengths of all the bus wiring paths cannot be set completely equal since some include the lengths of the vias while other do not. Therefore, there is a difference in delay of signal transmission among the wiring paths within the board. As a result, there is an increasing risk that a stable operation cannot be guaranteed in an operation beyond the gigabit speed.